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SA3488
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FEATURES
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SA3488
CMOS 256 X 256 DIGITAL SWITCHING MATRIX
Hardware (pin-to-pin) and software compatible with M088 and M3488 256 input and 256 output channel digital switching matrix Building block designed for large capacity electronic exchanges, subsystems and PABX Non-blocking single stage and higher capacity blocks (512 or 1024 channels) European and U.S. standard compatible (32/24 serial channels per frame) PCM inputs and outputs mutually compatible
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Actual input-output channel connections stored and modified via an on chip 8-bit parallel microprocessor interface 6 main "Functions" or "Instructions" available Typical Bit Rate : 2Mbit/s Typical Synchronization Rate : 8KHz (time frame is 125s) 5V power supply with internally generated bias voltage MOS & TTL input/output levels compatible
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DESCRIPTION The SA3488 is a non-blocking digital switching matrix that is capable of routing 256 input channels to any of 256 output channels. Data is fed into and out of the device via eight serial PCM input and output channels at 2MBits/sec. The device can connect or disconnect each input channel with any output channel, as well as carry out other functions which are user programmable via an eight bit parallel microprocessor interface. The SA3488 sees its primary use as a building block in high volume electronic exchanges, voice data PABX and other standard data communications applications. It can be easily configured for operation in PCM 24 or PCM 30 formats.
SA3488
PIN CONNECTIONS:
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SA3488 BLOCK DIAGRAM
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SA3488 ABSOLUTE MAXIMUM RATINGS * Symbol Parameter VCC VI VO Ptot Tstg Top Supply Voltage Input Voltage Off State Output Total Package Power Dissipation Storage Temperature Range Operating Temperature Range
Value -0.3 to 7 -0.3 to 7 7 1.5 -40 to +125 0 to +70
Unit V V V W C C
* Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other condition above those indicated in the operation sections of this specification, is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO CLOCK Freq. SYNC Freq. Top Parameter Supply Voltage Input Voltage Off State Input Voltage Input Clock Frequency Input Synchronization Operating Temperature Value 4.75 to 5.25 0 to 5.25 0 to 5.25 4.096 8 0 to 70 Unit V V V MHz KHz C
CAPACITANCES (Measuring freq. = 1MHz; Top = 0 to 70C; unused pins tied to VSS)
Symbol Parameter CI CI/0 C0 Input Capacitance I/O Capacitance
Pins 6 to 15; 26 to 30; 32 to 36 20 to 24
Min. Typ. Max. Unit 5 15 10 pf pf pf
Output Capacitance 1 to 4; 17 to 19; 37 to 40
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SA3488 D.C. ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70C, VCC = 5V 5%) All D.C. characteristics are valid 250s after VCC and clock have been applied.
Symbol Parameter VILC VIHC VIL Clock Input Low Level Clock Input High Level Input Low Level Pins 6 6 7 to 15 20 to 24 26 to 30 32 to 36 7 to 15 20 to 24 26 to 30 32 to 36 17 to 25 17 to 25 IOL = 1.8mA IOH = 250A 2.4 0.4 10 Test Condition Min. Typ. Max. Unit -0.3 2.4 -0.3 0.8 VCC 0.8 V V V
VIH
Input High Level
2.0
VCC V
VOL VOH VOL IIL
Output Low Level Output High Level
0.4
V V V A
PCM Output Low Level 1 to 4 IOL = 2.0mA 37 to 40 Input Leakage Current 6 to 15 VIN = 0 to VCC 26 to 30 32 to 36 17 to 24 VIN = 0 to VCC VCC applied; Pins 35 and 36 tied to VCC, after Device Initialization Clock Freq.= 4.096MHz
IDL
Data Bus Leakage Current
10
A
I CC
Supply Current
16
180
mA
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SA3488
A.C. ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70C, VCC = 5V 5%) All A.C. characteristics are valid 250s after VCC and clock have been applied. CL is the max. capacitive load and RL the test pull up resistor. Signal CK (clock) Symbol tCK tWL tWH tR tF tSL t HL tSH tWH tS tH tPDmin tPDmax tSL t HL tSH tWH tWL tWH t REP tSH t HH tR tF RD tWL tWH t REP tSH t HH tR tF Parameter Test Condition Clock Period Clock Low Level Width Clock High Level Width Rise Time Fall Time Low Level Setup Time Low Level Hold Time High Level Setup Time High Level Width Setup Time Hold Time Propagation time CL = 50pf,R L=2K referred to CK low level Propagation time CL = 50pf,R L=2K referred to CK high level Low Level Setup Time Low Level Hold Time High Level Setup Time High Level Width Low Level Width High Level Width Repetition Interval tREP = 40+2 tCK + between Active Pulses + tWL(CK) + High Level Setup Time + tR(CK) to Active Read Strobe High Level Hold Time from Active Read Strobe Rise Time Fall Time Low Level Width High Level Width Repetition Interval tREP = 40+2 tCK between Active Pulses + tWL + tR High Level Setup Time to Active Read Strobe High Level Hold Time from Active Write Strobe Rise Time Fall Time Min. 230 100 100 Typ. Max. Unit ns ns ns 25 ns 25 ns ns ns ns ns ns ns ns 200 100 50 90 tCK 150 tCK see formula 0 20 60 60 180 tCK see formula 0 20 60 60 ns ns ns ns ns ns ns
SYNC
PCM input Busses PCM Output Busses RESET
80 40 80 tCK -5 45 45
WR
ns ns ns ns ns ns
ns ns ns ns
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SA3488 A.C. ELECTRICAL CHARACTERISTICS (Cont.)
Signal CS1, CS2 Symbol tSL(CS-WR) tHL(CS-WR) tSH(CS-WR) tHH(CS-WR) tSL(CS-RD) t HL(CS-RD) tSH(CS-RD) tHH(CS-RD) C/D tS(C/D-WR) t H(C/D-WR) tS(C/D-WR) t H(C/D-WR) A1,S1, A2,S2 (match inputs) tS(match-WR) tH(match-WR) tS(match-RD) tH(match-RD) DR (data ready) tW t PD Parameter Low level setup time to WR falling edge Low level hold time from WR rising edge High level setup time to WR falling edge High level hold time from WR rising edge Low level setup time to RD falling edge Low level hold time from RD rising edge High level setup time to RD falling edge High level hold time from RD rising edge Setup time to write strobe end Hold time from write strobe end Setup time to read strobe start Hold time from read strobe end Setup time to write strobe end Hold time from strobe end Setup time to read strobe start Hold time from read strobe end Low state width DR output delay from write strobe end (active command) Instructions 5,6 Instructions 5, CL= 50pf 5.tCK Test Conditions Active Case Active Case Inactive Case Inactive Case Active Case Active Case Inactive Case Inactive Case Min. Typ. 0 0 0 0 0 0 0 0 Max. Unit ns ns ns ns ns ns ns ns
130 25 20 25 130 25 20 25 2 tCK 14 tCK
ns ns ns ns ns ns ns ns ns
ns
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SA3488 A.C. ELECTRICAL CHARACTERISTICS (Cont.)
Signal D0 to D7 (Interface bus) Symbol t S(BUS-WR) tH(BUS-WR) tPD(BUS) tHZ(BUS) Parameter Input setup time to write strobe end Input hold time from write strobe end Propagation time from (active) falling edge of read strobe Propagation time from (active)rising edge of read strobe to high impedance state Test Conditions Min. Typ. 130 25 CL= 200pf 120 Max. Unit ns ns ns
80
ns
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SA3488 PIN DESCRIPTION Pin 17 18 19 20 21 22 23 24 30 Designation D7 D6 D5 D4 D3 D2 D1 D0 C/D Description Bidirectional data bus used to transfer data and instructions to and from the microprocessor. The output bus is 8 bits wide and the input 5 bits wide. D0 is the least significant digit. The bus is tristate and is not available for use while RESET is held low.
33 34
CS2 CS1
26 27 29
S2 A2 A1
35
WR
In a write operation C/D = 0 qualifies bus content as data, while C/D = 1 qualifies it as a opcode. In a read operation C/D = 0 selects OR1 whereas C/D = 1 selects OR2. Chip select pins. Enable the device to perform valid read and write operations (active low). The two pins allow for row column selection for different types of microprocessors; normally though one is tied low. Address select or match pins. With S1 and S2 hardwired to ground or V CC, signals on A1 and A2 give rise to a 28S1 matched or unmatched condition i.e. S1=A1, S2=A2 =>a matched condition. Since in a matrix structure, devices in the same row share the same PCM output bus, instructions pertaining to channel connections (matched condition), must be processed as channel disconnections in the other devices (unmatched condition). Two channels can therefore never collide. When CS1 and CS2 are low, WR enables data transfer from the microprocessor to the device. Data, opcode and control signals are latched on the rising edge of WR. To ensure simultaneous instruction execution in a multichip configuration the WR rising edge must be 20 to 20 + tWL(CK) nsec late relative to the clock falling edge. When CS1 and CS2 are low and a matched condition exists, a low level on RD enables OR1 or OR2 for a read operation. In addition the rising edge of RD latches C/D and the matched condition pins in order to direct the internal flow of operations. In a multichip configuration the sametiming requirement must be met as in the WR case. sames
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RD
SA3488 Pin Description (Cont.) Pin 32 Designation RESET Description This pin is used to initialise the device. The initialisation routine takes one time frame whatever the RESET pulse width (one clock cycle minimum). All internal registers are set 'high' and the control memory is set to all 'ones' i.e. channel disconnection. The data bus is pulled to a high impedance state as well as the PCM output channels. DR is the data ready pin which is normally high. If DR goes low the following information is available via this pin. 1. Invalid instruction code (The pin is held low until a valid instruction is loaded). 2. An active output channel was found in a matrix of devices with the same CS pins during the execution of instruction 5. DR is low for two clock cycles. 3. Status register 2 was loaded with the total number of messages in time slot 0 during the execution of 6. DR is active low for two clock cycles. Input clock frequency is typically 4.096Mhz. This signal will set the internal input/ output channel bit rate to 2.048 Mbits/sec. The bit rate is set by division of the master clock frequency. The input synchronisation signal frequency is 8kHz and is active low. Internally generated time bases that maintain sequential addressing are synchonised via the SYNC signal. The input PCM bus accepts a standard data rate of 2MBits/ sec.
25
DR
instruction 6 CLOCK
7
SYNC
8 9 10 11 12 13 14 15
INP PCM7 INP INP INP INP INP INP INP PCM6 PCM5 PCM4 PCM3 PCM2 PCM1 PCM0
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SA3488 Pin Description (Cont.) Pin Designation Description Output PCM channel bit rate is also 2MBits/sec. The OUT PCM6 buffers are open drain simulating a wired 39 OUT PCM5 This minimises current spike problems in 40 OUT PCM4 configurations. Input and output channels 1 OUT PCM3 such a manner as to reduce any analogue Time delay max = 1 bit time-(clock high prop. time - Clock low prop. time). Internally generated bias voltage (-2.5 to -3.0V for VCC in the operating range). A maximum of 220pf capacitor connected to pin 5 provides improved filtering. 37 OUT PCM7 output 38 OR connection. multichip are driven in delay time up to: 2 OUT PCM2 3 OUT PCM1 4 OUT PCM0 5 BIAS
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SA3488
FUNCTIONAL OVERVIEW The SA3488 is intended for large telephone switching systems, mainly central exchanges, digital line concentrators and private branch exchanges where a distributed microcomputer control approach is extensively used. It consists of a speech memory (SM), a control memory (CM), a serial/parallel and a parallel/serial converter, an internal parallel bus, an interface (8 data lines, 11 control signals) and dedicated logic. By means of repeated clock division two time bases are generated. These are preset from an external synchronization signal to two specific count numbers so that sequential scanning of the bases give synchronous addresses to the memories and I/O channel controls. Different preset count numbers are needed because of processing delays and data path direction. The time-base for output channels is advanced with respect to the actual time. Each serial PCM input channel is converted to parallel data and stored in the speech memory at the beginning of any new time slot (according to first timebase) in the location determined by input pin number and time slot number. The control memory CM maintains the correspondences between input and output channels. More exactly, for any output pin/output channel combination the control memory gives either the full address of the speech memory location involved in the PCM transfer or an 8-bit word to be supplied to the parallel/serial output converter. A 9th bit at each CM location defines the data source for output links; low for SM, high for CM. The late timebase is used to scan the output channels and to determine the pins to be serviced within each channel. Enough idle cycles are left to the microprocessor for synchronous instruction processing. Two 8-bit registers OR1 and OR2 supply feedback data for control or diagnostic purposes; OR1 comes from the internal bus i.e. from memories, while OR2 gives an opcode copy and additional data to the microcomputer. A four byte, 5-bit stack register and an instruction register, under microcomputer control, store input data available at the interface. Dedicated logic, under control of the microprocessor interface, extracts the 0 channel content of any selected PCM input bus, using spare cycles of SM.
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SA3488
FUNCTIONAL DESCRIPTION OF SPECIFIC MICROPROCESSOR OPERATIONS The device, under microprocessor control, performs the following instructions: 1 CHANNEL CONNECTION/DISCONNECTION 2 CHANNEL DISCONNECTION 3 INSERTION OF A BYTE ON A PCM OUTPUT CHANNEL/CHANNEL DISCONNECTION) 4 TRANSFER OF A SINGLE OUTPUT CHANNEL SAMPLE 5 TRANSFER OF A SINGLE OUTPUT CHANNEL CONTROL WORD 6 TRANSFER OF SELECTED 0 CHANNEL PCM INPUT DATA ACCORDING TO AN 8-BIT MASK PREVIOUSLY STORED IN THE "EXPECTED MESSAGES" REGISTER. The instruction flow is as follows: Any input protocol is started by the microprocessor interface loading the internal stack register with 2 bytes (4 bytes for instructions 1 and 3) qualified as data bytes by C/D = 0 and a specific opcode qualified by C/D = 1 (match condition is normally needed). After the code is loaded, the instruction register is immediately checked to see whether it is acceptable; if not, it is rejected. If accepted the instruction is also processed as regards match condition and is appended for execution during the memories' space cycles. Four cases are possible: a) the code is not valid; execution cannot take place, the DR output pin is reset to indicate the error and all registers are saved; b) the code is valid for types 2, 4 and 6 but it is unmatched; execution cannot take place, and DR is not affected. c) the code is valid for types 1 and 3 and it is unmatched; the instruction is interpreted as a channel disconnection. d) the code is valid and it either matches or is of type 5; the instruction is processed as received. Validation control takes only two cycles out of a total execution time of 5 to 13 cycles; the last operation is the updating of the contents of registers OR1 and OR2.
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SA3488
During a very long internal operation (device initialization after RESET going high or execution of instruction 6) a new set of data bytes with a valid opcode is accepted while a wrong code is rejected. At the end of the current routine execution takes place in the same way as described before. At the end of an instruction it is normally recommended to read one or both registers. To enable instruction 6, however, it is necessary to read register OR2. This is because instruction 6, used between other short instructions of type 1 to 5, must have a lower priority and can be enabled only after the short instructions have been completed. Instruction 6 normally has a long process and a special flow which is described below. First a not-all-zero mask is stored in the "expected messages" register and in another "background" register. This operation starts the second phase of instruction 6 which is called "channel 0 extraction" and is repeated at the beginning of any new time frame. At the beginning of the time frame a new copy of activated channels to be extracted is made from the "background register" and put in the "expected messages" register. In addition the latter register is modified to indicate the exact number of messages that have arrived. The term messages covers any input 0 channel data with starting sequence different from the label 01. So using this label the number of expected messages can be reduced to correspond to the number of effective messages. If and only if the residual number is different from zero will the device start the extraction protocol at the end of the current routine. The procedure is as follows: the DR output is pulsed low as a two cycle interrupt request and OR2 is loaded with the total number of active channels to be extracted. The transfer of OR2 contents to the microprocessor continues the extraction which consists of repeated steps of OR1 and OR2 loading, indicating respectively the message and the incoming bus number. Reading the registers in the order OR1, OR2 must be continued until completion or until the time frame runs out. With a new time frame a new extraction process begins, resuming the copy operation from the background register. During extraction the active channels are scanned from the highest to the lowest number (from 7 to 0). While extraction is being carried out the time interval requirements between active rising edges of RD are a minimum of 5 to 13 tCK for sequence OR2 - OR1 and a minimum of 3 times tCK for sequence OR1 - OR2. More details are given in the following tables.
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SA3488
INSTRUCTION TABLES The most significant digits of OR2 A7, A6, A5 are a copy of the PCM selected output bus; the least significant digits or OR2 are the opcode while C8 is the control bit. In all cases parentheses () define actual register contents. INSTRUCTION 1: CHANNEL CONNECTION/DISCONNECTION
Control Signals Match C/D CS X X X X 0 0 0 0 0 0 0 0 0 0 WR RD 0 0 0 0 0 1 1 1 1 1 1 0 D7 X X X X X D6 X X X X X Data Bus D5 X X X X X D4 X Ci4 X D3 X Ci3 X D2 Bi2 Ci2 D1 Bi1 D0 Bi0 Notes 1st Data Byte:selected input bus 2nd Data Byte: selected input channel
Ci1 Ci0
Bo2 Bo1 Bo0 3rd Data Byte: selected output bus
Co4 Co3 Co2 Co1 Co0 4th Data Byte: selected output channel X 0 0 0 1 Instruction Opcode
Yes/No 1 Yes 0
C7 C6 (1 1 (Bi2 Bi1
C5 C4 C3 C2 C1 C0 0R1 : CM content copy, 1 1 1 1 1 1) that is for mismatch Bi0 Ci4 Ci3 Ci2 Ci1 Ci0) condition or match condition 0 0 0 0 0 0 0 0 0 1 1) 1) OR2
Yes
1
0
1
0
A7 A6 A5 C8 (Bo2 B01 Bo0 1 (Bo2 Bo1 Bo0 0
INSTRUCTION 2: OUTPUT CHANNEL DISCONNECTION
Control Signals Match C/D CS X X Yes Yes Yes 0 0 1 0 1 0 0 0 0 0 WR RD 0 0 0 1 1 1 1 1 0 0 D7 X X X 1 D6 X X X 1 Data Bus D5 X X X 1 D4 X D3 X D2 D1 D0 Notes Bo2 Bo1 Bo0 1st Data Byte: selected output bus
Co4 Co3 Co2 Co1 Co0 2nd Data Byte: selected output channel X 1 0 1 0 0 0 1 0 0 1 1 1 1 0 1 0 0) Instruction Opcode OR1 : CM Content Copy (output channel is inactive) OR2
A7 A6 A5 1 (Bo2 Bo1 Bo0 1
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SA3488
INSTRUCTION 3: LOADING A MICROPROCESSOR BYTE
Control Signals Match C/D CS X X X X 0 0 0 0 0 0 0 0 0 0 WR RD 0 0 0 0 0 1 1 1 1 1 1 0 D7 X X X X X D6 X X X X X Data Bus D5 X X X X X D4 X Ci4 X D3 X Ci3 X D2 D1 D0 Ci5 Ci0 Notes 1st Data Byte: most significant digits to be inserted 2nd Data Byte: least significant digits to be inserted Ci7 Ci6 Ci2 Ci1
Bo2 Bo0 Bo1 3rdData Byte: selected output bus
Co4 Co3 Co2 Co1 Co0 4th Data Byte: selected output channel X 0 1 0 0 Instruction Opcode
Yes/no 1 Yes 0
Yes
1
0
1
0
C7 C6 C5 C4 C3 C2 C1 C0 OR1 : CM (1 1 1 1 1 1 1 1) content copy, that (Ci7 Ci6 Ci5 Ci4 Ci3 Ci2 Ci1 Ci0) is for mismatch condition or match condition A7 A6 A5 1 0 1 0 0 OR2 (Bo2 Bo1 Bo0 1 0 1 0 0)
INSTRUCTION 4: TRANSFER OF A SINGLE PCM SAMPLE
Control Signals Match C/D CS X X Yes Yes 0 0 1 0 0 0 0 0 WR RD 0 0 0 1 1 1 1 0 D7 X X X C7 S7 D6 X X X C6 S6 Data Bus D5 X X X C5 S5 D4 X D3 X D2 D1 D0 Notes Bo2 Bo1 Bo0 1stData Byte: selected output bus
Co4 Co3 Co2 Co1 Co0 2ndData Byte: selected output channel X C4 S4 1 C3 S3 1 1 0 C2 S2 0 0 1 C1 S1 1 1 1 C0 S0 1 1) Instruction Opcode OR1 : CM Content Copy if C8= 1; or SM Content Sample if C8=0 OR2
Yes
1
0
1
0
A7 A6 A5 C8 (Bo2 Bo1 Bo0 C8
Note: S7..S0 is a parallel copy of the PCM data; S7 is the most significant digit and the first of the sequence.
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SA3488 INSTRUCTION 5: TRANSFER OF AN OUTPUT CHANNEL CONTROL WORD
Control Signals Match C/D CS X X X Yes Yes 0 0 1 0 1 0 0 0 0 0 WR RD 0 0 0 1 1 1 1 1 0 0 D7 X X X C7 D6 X X X C6 Data Bus D5 X X X C5 D4 X D3 X D2 D1 D0 Notes Bo2 Bo1 Bo0 1st Data Byte: selected output bus
Co4 Co3 Co2 Co1 Co0 2nd Data Byte: selected output channel X C4 1 C3 1 1 0 C2 0 0 0 C1 0 0 0 Instruction Opcode C0 OR1 : CM selected CM word copy 0 0) OR2
A7 A6 A5 C8 (Bo2 Bo1 Bo0 C8
INSTRUCTION 6: CHANNEL 0 SELECTION MASK STORE/DATA TRANSFER
Control Signals Match C/D CS X X Yes Yes Yes Yes Yes 0 0 1 0 1 0 1 0 0 0 0 0 0 0 WR RD 0 0 0 1 1 1 1 1 1 1 0 0 0 0 D7 X X X D6 X X X Data Bus D5 X X X D4 X D3 X D2 D1 D0 Notes Mi7 Mi6 Mi5 1st Data Byte: most significant digits of selection mask
Mi4 Mi3 Mi2 Mi1 Mi0 2nd Data Byte: most significant digits of selection mask X 1 1 1 0 Instruction Opcode OR1 : register is not affected 1 1 1 0 OR2 : see below OR1 : register is not affected 1 S3 1 1 S2 1 1 S1 1 0 S0 0 OR2 : see below OR1 : expected message stored in SM OR2
Mask store control (previous content) N2 N1 N0 Tn
First Data Transfer (after DR going low) (previous content) N2 N1 N0 Tn
Repeated Data Transfer (after first OR2 transfer) Yes 0 0 1 0 S7 S6 S5 S4 Yes 1 0 1 0 P2 P1 P0 Fn
Notes: 1. Regarding mask bits Mi0 to Mi7 a logic "0" level means disabling condition, a logic "1" level means enabling condition. 2. A null mask or a RESET pulse clears the mask and the deep background mask registers and disable channel 0 extraction function. 3. Reading of OR2 is optional after mask store or redefinition, because function is activated only by notnull mask writing. 4. After mask store (N2 N1 N0) is the sum of activated channels, after DR is the sum of active channels; Tn=1/0 means activation/suppression of the function after store while after DR only Tn = 1 can appear indicating non-null configuration extraction. 5. Reading of OR2 is imperative after DR in order to step the data transfer; reading of OR1 is also needed to scan in descending order the priority register. Relevant messages only are considered, i.e. only messages with a MSD label different from 0 1. 6. (P2 P1 P0) is the PCM bus on which the message copied in OR1 was found; Fn is a continuation bit telling respectively on level 1/0 for any more/no more extraction to be performed.
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SA3488 PCM TIMING, RESET
WRITE OPERATION TIMING
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SA3488 READ OPERATION TIMING
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SA3488 Notes:
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SA3488
Disclaimer: The information contained in this document is confidential and proprietary to South African MicroElectronic Systems (Pty) Ltd ("SAMES") and may not be copied or disclosed to a third party, in whole or in part, without the express written consent of SAMES. The information contained herein is current as of the date of publication; however, delivery of this document shall not under any circumstances create any implication that the information contained herein is correct as of any time subsequent to such date. SAMES does not undertake to inform any recipient of this document of any changes in the information contained herein, and SAMES expressly reserves the right to make changes in such information, without notification,even if such changes would render information contained herein inaccurate or incomplete. SAMES makes no representation or warranty that any circuit designed by reference to the information contained herein, will function without errors and as intended by the designer.
Any Sales or technical questions may be posted to our e-mail address below: energy@sames.co.za For the latest updates on datasheets, please visit out web site: http://www.sames.co.za South African Micro-Electronic Systems (Pty) Ltd P O Box 15888, 33 Eland Street, Lynn East, 0039 Koedoespoort Industrial Area, Republic of South Africa, Pretoria, Republic of South Africa Tel: Fax: 012 333-6021 012 333-8071 sames
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Int +27 12 333-6021 Int +27 12 333-8071

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